The present invention relates to a thin-film semiconductor device comprising a non-single-crystal semiconductor film, a method of fabricating such a thin-film semiconductor device, and a display system in which the thin-film semiconductor device is used.
Thin-film semiconductor devices formed using non-single-crystal semiconductor films such as polycrystalline and amorphous semiconductor films are used in the display portions and peripheral circuitry of active matrix liquid crystal display devices, image sensors and SRAM devices. xe2x80x9cThin film semiconductor devicexe2x80x9d refers to a semiconductor film, a thin-film transistor (TFT), or a CMOS type of TFT having a p-channel TFT and an n-channel TFT. xe2x80x9cThin-film semiconductor devicexe2x80x9d and xe2x80x9cTFTxe2x80x9d are used interchangeably in this document.
Thin-film semiconductor devices are required to operate at high speeds when used in peripheral circuitry such as a liquid crystal display device. When the operational speed is sufficiently high, switching devices of the display portion and all the peripheral circuitry such as shift registers and analog switches can be integrated onto the liquid crystal substrate using the suitable thin-film semiconductor devices.
If the speed of the thin-film semiconductor devices were to be increased, the range of applications would be much wider than in the prior art. Prior art applications of the thin-film semiconductor devices are limited to liquid crystal display devices. It has been very difficult to extend the application of thin-film semiconductor devices to digital and analog circuits where single-crystal MOSFETs are used. This is because the thin-film semiconductor device has a smaller carrier mobility than the carrier mobility of a single-crystal MOSFET. Thus, the speed of the thin-film semiconductor device is slower than the speed of the single crystal MOSFET. However, if the thin-film semiconductor device operates at a speed comparable to that of a single-crystal MOSFET, the thin-film semiconductor device may be used in digital and analog circuits where only single-crystal MOSFETs are used in the prior art.
The thin-film semiconductor device differs from a single-crystal MOSFET in that it is formed on an insulating substance. This means that it is not affected by the problems experienced by the single-crystal MOSFET. Problems such as noise transmitted through the substrate and latch-up caused by current flowing through the substrate are examples. Therefore, increasing the speed of a thin-film semiconductor device is a technical objective.
In order to increase the speed of the thin-film semiconductor device, the following problems described must be solved. An example of a thin-film semiconductor device is shown in FIG. 56A and an equivalent circuit diagram of this thin-film semiconductor device is shown in FIG. 56B. In FIG. 56B, Rc1 and Rc2 are contact resistances of a contact portion 412 between wiring 408 and a source portion 404 and a contact portion 414 between wiring 410 and a drain portion 406. Rs is the source resistance of the source portion 404, Rch is the channel resistance of a channel portion 402, and Rd is the drain resistance of the drain portion 406.
In order to increase the speed of this thin-film semiconductor device, it is first necessary to reduce the total value of the serially connected resistances Rc1, Rs, Rch, Rd, and Rc2 when the transistor is ON. If the total resistance when the transistor is ON is denoted by Ron, Ron is the sum of the on-state channel resistance Rch(on) and the overall parasitic resistance Rp of the rest of the components. In other words:   "AutoLeftMatch"                              Ron          =                                    Rch              ⁡                              (                on                )                                      +            Rp                                                        =                                    Rch              ⁡                              (                on                )                                      +                          (                              Rc1                +                Rs                +                Rd                +                Rc2                            )                                          
Therefore, in order to achieve a faster thin-film semiconductor device, both the on-state channel resistance Rch(on) and the overall parasitic resistance Rp must be reduced. In order to reduce Rch(on), it is necessary to find new methods to fabricate the semiconductor films which form the thin-film semiconductor device. More specifically, the carrier mobility of the semiconductor films must be increased and the channel portion 402 must be shortened.
The resistances Rs and Rd may be reduced by either increasing the impurity concentration of the source portion and the drain portion or improving the quality of the semiconductor films forming the source and drain portions. To reduce Rc1 and Rc2, barrier metal can be placed at the contact portions 412 and 414. However, it is more effective to simplify the fabrication process by increasing the impurity concentration of the source and drain portions rather than using barrier metal.
The carrier mobility of the semiconductor films are increased by forming the thin-film semiconductor device using polycrystalline silicon (polysilicon). A polycrystalline silicon thin-film semiconductor device generally has carrier mobility of at least approximately 10 cm2/V.s, which is far higher than that of an amorphous silicon thin-film semiconductor device.
Three fabrication methods are known in the prior art for fabricating a polycrystalline silicon thin-film semiconductor device of this type, as described below. In the first fabrication method, a polycrystalline silicon film is first deposited by a low-pressure chemical vapor deposition (LPCVD) method at a deposition temperature of approximately 600xc2x0 C. or more. The size of the regions (islands) of the polycrystalline silicon ranges approximately from 20 nm to 80 nm. The polycrystalline silicon film surface is then thermally oxidized to form the semiconductor layer and gate insulation layer of the thin-film semiconductor device. The boundary surface roughness (center line average height, Ra) between the gate insulation film and gate electrode is at least approximately 3.1 nm. One example of an n-channel type thin-film transistor fabricated by this method has a carrier mobility of approximately 10 cm 2/V.s to 20 cm2/V.s. The average grain area of the semiconductor film is approximately 4,000 to 6,000 nm2.
In the second fabrication method, an amorphous silicon film is first formed by plasma-enhanced CVD (PECVD). The amorphous silicon film is then annealed in a nitrogen atmosphere at the temperature of 600xc2x0 C. from about 20 hours to 80 hours. This annealing process converts the amorphous silicon film into a polycrystalline silicon film known as solid-phase crystallization method. The surface of this polycrystalline silicon film is thermally oxidized to form a semiconductor layer and gate insulation layer of the thin-film semiconductor device. After the thin-film semiconductor device is structured, a hydrogen plasma is applied. In this case, an n-channel type thin-film transistor has the carrier mobility of approximately 150 cm2/V.s. See S. Takenaka, et al., Jpn. J. Appl. Phys. 29, L2380 (1990).
In the third fabrication method, a polycrystalline silicon film is first deposited by LPCVD at a deposition temperature of 610xc2x0 C. Si+ is implanted into the polycrystalline silicon film at a dose of approximately 1.5xc3x971015 cmxe2x88x922, which converts the polycrystalline silicon film into an amorphous film. The film is then annealed at 600xc2x0 C. in a nitrogen atmosphere from tens to several hundreds of hours, so that the amorphous silicon is recrystallized into a polycrystalline silicon film. The surface of this polycrystalline silicon film is then thermally oxidized to form a semiconductor layer and gate insulation layer of the thin-film semiconductor device. After the basic structure of the thin-film semiconductor device is completed, a hydrogenated silicon nitride (p-Si N:H) film is deposited by PECVD over the device, and then the device is annealed in a furnace at 400xc2x0 C. to hydrogenate the device. In this case, an n-channel type thin-film transistor has the carrier mobility of approximately 100 cm2/V.s. See T. Noguchi, et al., J. Electrochemical Soc., 134, page 1771 (1987).
The three fabrication methods described above have inherent problems. The second fabrication method provides a thin-film semiconductor device with high carrier mobility, but requires several tens of hours of furnace annealing after the amorphous silicon film is deposited. This process seriously reduces productivity because of the long process time. In addition, a large quantity of particles are generated in the reaction chamber by the PECVD. These particles cause a large number of device defects because they fall on the substrate during the deposition. Therefore, the yield is very poor.
The third fabrication method requires even longer furnace annealing and has a more complicated process than the second fabrication method. If the number of process steps is increased by even one step, the product yield is reduced. The need for several tens of hours to several hundreds of hours of furnace annealing is unrealistic from the mass-production point of view, and is thus not practicable.
The first fabrication method involves the simple method of depositing a polycrystalline silicon film by LPCVD and then forming a thin-film semiconductor device by thermal oxidation. This method is extremely simple and stable and thus well adapted for mass production. However, the first fabrication method produces small average grain area of approximately 4,000 to 6,000 nm2 and low carrier mobility of 10 cm2/V.s to 20 cm2/V.s.
The reduction of the contact resistance Rc and the resistances Rs and Rd is described below. TFTs include ordinary TFT structure and a lightly doped drain (LDD) TFT structure. In order to reduce the overall parasitic resistance Rp and the total ON resistance Ron, the LDD-type TFT is preferred.
A method of fabricating ordinary TFTs is described with reference to FIG. 27. In this fabrication method, a gate insulation film 25 is first formed on thin semiconductor films 22 that have been patterned into islands on an insulating substrate 21 and gate electrodes 26 are formed over the semiconductor films 22. Next, donor impurity ions are implanted at high concentration into the thin semiconductor film 22 to form the source and drain regions of the n-channel TFT and form thin n+ semiconductor films 23. Acceptor impurity ions are implanted at high concentration into the thin semiconductor film 22 which are the source and drain regions of the p-channel TFT and form thin p+ semiconductor films 24. Since this method implants the impurities by using the gate electrode as a channel mask, the resultant TFT is called a self-aligned TFT. A non-self-aligned TFT is produced by first forming the thin n+ semiconductor islands and the thin p+ semiconductor islands that contain appropriate impurities. These TFTs are covered with an interlayer insulation film 27, and then thin metal films 28 are patterned to complete the TFTs.
Single-crystal MOSFETs possessing LDD structure are widely used in semiconductor integrated circuits which are made using single-crystal substrates. The LDD MOSFETs restrain the device from generating hot carriers and have high reliability. Conventional fabrication techniques of LDD-type MOSFETs are described in JP 2-58274, JP 2-45972, JP 62-241375 and JP 62-234372.
Since the diffusion coefficient of the impurities in the single-crystal semiconductor material is low, the LDD length can be shortened to approximately one-tenth of the channel length. Therefore, the source-drain current of the transistor on-state (ON-current) of an LDD-type MOSFET is reduced to only about one-tenth of that of an ordinary-structure MOSFET.
In contrast, since TFTs use non-single-crystal thin semiconductor films, the impurity ions have increased diffusion along the grain boundaries of the semiconductor films. The actual diffusion coefficient in poly-Si (polysilicon) films increases by at least one order of magnitude over the diffusion coefficient in the single-crystal semiconductor. Therefore, the LDD length of the LDD-type TFT is long. The longer LDD results in high electric resistance of this LDD portion which cause the ON current to be one-half or less than that of an ordinary TFT structure. For this reason the LDD-type TFT has not been used in circuits that require high speeds.
In the self-aligned ordinary TFTs shown in FIG. 27, impurities are implanted at high concentration into the source and drain portions. Therefore, the parasitic resistance at the source and drain regions is low. However, other problems prevent increasing the speed of the self-aligned ordinary TFTs. The increased diffusion along the grain boundaries. increases a parasitic capacitance of the TFT between the gate and the source/drain overlapped regions which results in an increase of MOS capacitance.
As shown in FIG. 27, an overlapping portion of the n-channel TFT indicated by Yjn and an overlapping portion of the p-channel TFT indicated by Yjp form parasitic capacitances. The effective n-channel channel length Leffn and the effective p-channel channel length Leffp are the lengths obtained by subtracting twice the corresponding overlapping portion Yjn or Yjp from the n-channel gate electrode length, Lgaten or the p-channel gate electrode length Lgatep for the p-channel device. These gate electrode lengths are also known as gate electrode widths.
For an effective channel length of 4 xcexcm, a gate electrode length of at least 6 xcexcm is required because these overlapping portions are at least 1 xcexcm long. The increase in the parasitic capacitance of the TFTs is at least a factor of 1.5 compared to the originally desired device. This results in a reduced operating speed of two-thirds or less of the speed of the originally desired TFT. Accordingly, ordinary self-aligned TFTs of the prior art are not used to increase operating speeds.
The prior art technique described in JP 5-173179 uses the ordinary TFTs shown in FIG. 27 for the peripheral circuitry because the LDD-type TFTs are not suitable for high-speed operation. LDD-type TFTs are used in the display portion because the liquid crystal of this display portion is a high-resistance material. Thus, it is necessary to restrain the OFF current of the pixel TFTS.
Another prior art using the LDD-type TFTs in the peripheral circuitry and the display portion is described in JP 6-102531. However, even in this prior art, the ON current of each LDD-type TFT is small. The ON current is increased by adding novel processing steps such as solid-phase crystallization and hydrogenation. See page 7, left column, lines 26 to 36 of JP 6-102531.
Although the utilization of the LDD structure has the advantage of preventing leakage currents, additional processing steps must be introduced to compensate for the low ON-current inherent in the LDD structure. JP 6-102531 discloses that the impurity dose implanted into the LDD region is 1xc3x971014 cmxe2x88x922 or less. See page 5, left column, lines 45 to 48. This numerical limit is not intended for optimizing the ON/OFF current ratio but for reducing the OFF current and restraining leakage currents.
Therefore, the ON current cannot be increased even though the OFF current can be reduced because, as the impurity dose implanted into the LDD region becomes smaller, the resistance of this LDD region increases and the ON current decreases. Similarly, the impurity dose implanted into the source and drain portions is disclosed to be in the range of between 1xc3x971014 and 1xc3x971017 cmxe2x88x922. See page 5, right column, lines 11 to 14 of JP 6-102531. This numerical limit is neither intended for optimizing the diffusion length due to increased diffusion, nor reducing the resistances Rc, Rs, and Rd. Furthermore, the channel length is set to 6 xcexcm and no technique is disclosed for reducing the channel length of the TFT to 5 xcexcm or less.
As described above, it is difficult to increase the ON current, and to reduce the parasitic resistances Rc, Rs, and Rd while optimizing the diffusion length. Further, it is difficult to reduce channel length. Therefore, it is difficult to apply LDD-type TFTs to high-speed circuits without additional processing steps such as solid-phase crystallization.
An objective of the invention is the provision of a thin-film semiconductor device which can be fabricated by a simple, effective process and which also has good characteristics. A method of fabricating such a thin-film semiconductor device and a display device using this thin-film semiconductor device is provided.
Another objective of the invention is to provide an LDD-type thin-film semiconductor device that is capable of operating at high speed without requiring any additional processing steps. The invention also provides a method for fabricating such a thin-film semiconductor device and a display device using this thin-film semiconductor device.
A further objective of the invention is to provide higher speeds for thin-film semiconductor devices, and to provide a thin-film semiconductor device that replaces single-crystal MOSFETS used in the digital and analog circuits thus broadening the field of application for the thin-film semiconductor devices. A method of fabricating this thin-film semiconductor device is also provided.
A first aspect of the invention provides a method of fabricating a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate. This method includes a step of depositing a semiconductor film by a chemical vapor deposition method under conditions that retard the generation rate of nuclei that act as seeds for film formation and accelerate the growth rate of islands formed from the nuclei.
This first aspect of the invention accounts for the fact that nucleus generation and island growth are competing processes. Retarding the nucleus generation rate while accelerating the island growth rate during the deposition of a semiconductor film ensures that the islands grow fast to cover the insulating material portion before a large number of nuclei are generated on the insulating material portion. This ensures that the island regions are large, so that it is possible to enlarge the area of the grains which appear after the semiconductor film is annealed. This enables an increase in the carrier mobility of the thin-film semiconductor device.
Another effect of making the island regions large is the way in which the semiconductor film surface becomes smooth. Thus, the present invention enables a dramatic improvement in the characteristics of a thin-film semiconductor device using an extremely simple process, in which a silicon film is formed by a chemical vapor deposition method alone, and without using complicated and unnecessary processes such as silicon ion implantation, lengthy furnace annealing, or hydrogenation. The semiconductor film deposited by this embodiment is not limited to an amorphous film.
The nucleus generation rate is controlled by the deposition temperature and the island growth rate is controlled by the deposition rate. The deposition temperature is preferred to be approximately 580xc2x0 C. or less and the deposition rate is preferred to be approximately 6 xc3x85/minute or more. Thus, the island regions can be made extremely large by setting the deposition temperature and deposition rate to within the above ranges. The nucleus generation rate could be controlled by a suitable choice of the type of substrate. The deposition rate could be determined by the flow rate of the reactant gas or the deposition pressure.
A second aspect of the invention provides that the deposition temperature is preferably approximately 550xc2x0 C. or less. The average grain area is maximized by setting the deposition temperature to approximately 550xc2x0 C. or less.
A third aspect of the invention provides that the deposition temperature is preferably approximately 530xc2x0 C. or less. The defects within the crystals are reduced by setting the deposition temperature to approximately 530xc2x0 C. or less. The lower limit of the deposition temperature can be set to suit the type of reactant gas. For example, a lower deposition temperature is approximately 460xc2x0 C. for mono-silane or approximately 370xc2x0 C. for di-silane will produce the same results.
A fourth aspect of the invention provides that either mono-silane (SiH4) or di-silane (Si2H6) is used as at least one type of reactant gas while the semiconductor film is being deposited by the chemical vapor deposition method. The basic principle of the invention is not substantially affected by the type of reactant gas used, and thus other reactant gases may be used.
A fifth aspect of the invention provides a step of subjecting a surface of the semiconductor film to thermal oxidation, after the semiconductor film deposition step. This thermal oxidation provides an oxide film. If the semiconductor film is in an amorphous state, it is converted into a polycrystalline state.
A sixth aspect of the invention provides a step of irradiating the semiconductor film with optical energy or electromagnetic-wave energy, after a semiconductor film deposition step. The maximum processing temperature after the irradiation step is approximately 350xc2x0 C. or less. Using a low-temperature process allows using inexpensive glass as the substrate and prevents warping of the substrate under its own weight.
A step of annealing the semiconductor film at a temperature of approximately 600xc2x0 C. or less is included after the semiconductor film deposition step. The maximum processing temperature after the annealing step could be held to approximately 600xc2x0 C. or less. By combining this low-temperature process with solid-phase crystallization, a semiconductor film of an even higher quality is obtained. The maximum processing temperature after the annealing step is preferably approximately 350xc2x0 C. or less.
A seventh aspect of the invention provides a step of annealing the semiconductor film at a temperature in the range of between approximately 500xc2x0 C. and approximately 700xc2x0 C., after the semiconductor film deposition step. Annealing the semiconductor film in such a manner in accordance with the invention ensures that a semiconductor film in an amorphous state, can be converted it into a polycrystalline state at a comparatively low temperature. This makes it possible to obtain a thin-film semiconductor device having even better quality characteristics. The temperature range for the annealing in this case is preferably between approximately 550xc2x0 C. and approximately 650xc2x0 C.
An eighth aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, wherein the average grain area of the semiconductor film is at least approximately 10,000 nm2. Since the average grain area is large, the carrier mobility is increased enabling an increase in speed of the thin-film semiconductor device.
A ninth aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, wherein the average area of islands grown from nuclei that act as seeds for forming the semiconductor film is at least approximately 10,000 nm2.
Since the average island area is large, the average grain area after annealing is also large enabling an increase in speed of the thin-film semiconductor device. In addition, the invention provides the further advantage of a smooth semiconductor film surface.
A tenth aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material. portion which covers at least one portion of a surface of a substrate, wherein the boundary surface roughness (center line average height, Ra) between a gate insulation film formed by thermal oxidation of the semiconductor film and a gate electrode formed on the gate insulation film is no more than approximately 2.00 nm.
Since the center line average height Ra is no more than approximately 2.00 nm, the gate insulation film formed on the semiconductor film has a smooth surface, resulting in a high breakdown voltage between source and gate. This reduces the number of pixel defects, for example. In addition, the thermal oxidation temperature is reduced, enabling the implementation of both lower costs and high-density processing. Also, the low oxidation temperature extends the lifetime of the fabrication apparatus as well as ease their maintenance.
An eleventh aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the semiconductor film includes a first impurity-doped semiconductor film located in source and drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between drain and channel portions or between source and channel portions of the thin-film transistor. The maximum impurity concentration of the second impurity-doped semiconductor film is in the range of between approximately 1xc3x971018 cmxe2x88x923 and approximately 1xc3x971019 cmxe2x88x923.
The thin-film semiconductor device has an LDD structure with a shorter channel and thus operates at a higher speed. The breakdown voltage between source and drain is also heightened. The maximum impurity concentration of the second impurity-doped semiconductor film which is the LDD portion is optimized. The breakdown voltage is heightened by setting this maximum impurity concentration to be approximately 1xc3x971019 cmxe2x88x923 or less. The sheet resistance of the LDD portion is reduced and consequently the ON current is prevented from dropping by setting this maximum impurity concentration to approximately 1xc3x971018 cmxe2x88x923 or more. To achieve further optimization, the maximum impurity concentration is preferred to be in the range of between approximately 2xc3x971018 cmxe2x88x923 and approximately 5xc3x971018 cmxe2x88x923 which enables an optimum ratio between ON current and OFF current.
A twelfth aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the semiconductor film includes a first impurity-doped semiconductor film located in the source and drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor. The maximum impurity concentration of the first impurity-doped semiconductor film is in the range of between approximately 5xc3x971019 cmxe2x88x923 and approximately 1xc3x971021 cmxe2x88x923.
The maximum impurity concentration of the first impurity-doped semiconductor film is optimized. The diffusion of impurities from the source and the drain portions into the LDD portion is restrained and the breakdown voltage between the source and the drain portions of the thin-film semiconductor device is heightened by setting this maximum impurity concentration to be approximately 1xc3x971021 cmxe2x88x923 or less. Both the contact resistance and the source and the drain resistance are reduced, thus the operational speed of the thin-film semiconductor device is increased, when setting this maximum impurity concentration to be approximately 5xc3x971019 cmxe2x88x923 or more. To achieve further optimization, the maximum impurity concentration is set to be between approximately 1xc3x971020 cmxe2x88x923 and approximately 3xc3x971020 cmxe2x88x923. This enables faster operation of the devices and even further miniaturization of components, while increasing the breakdown voltage.
A thirteenth aspect provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the semiconductor film includes a first impurity-doped semiconductor film located in the source and the drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor. An LDD length in the drain portion or the source portion is in the range of between approximately 0.6 xcexcm and approximately 4 xcexcm.
The invention miniaturizes components by setting the LDD length to be approximately 4 xcexcm or less. An LDD length of approximately 0.6 xcexcm or more prevents the effective LDD length from being reduced to zero by the diffusion of the impurities from the source and the drain portions. Thus, further lowering of the breakdown voltage is prevented. To achieve further optimization, the LDD length is preferred to be between approximately 1 xcexcm and approximately 2 xcexcm.
A fourteenth aspect provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate where the semiconductor film includes a first impurity-doped semiconductor film located in the source and the drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor. The length of a gate electrode formed on the semiconductor film with a gate insulation film in between is approximately 5 xcexcm or less.
The channel is decreased in length as the gate electrode length is set to approximately 5 xcexcm or less. A reduction in the ON current caused by the LDD structure is sufficiently compensated enabling faster operation of the devices. The gate electrode length is preferably approximately 3 xcexcm or less. Such a short channel length further increases the operational speed of the device and also reduce the supply voltage to the device.
A fifteenth aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the semiconductor film includes a first impurity-doped semiconductor film located in the source and the drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor. When an LDD length of a drain portion is Llddd and the distance from an edge of the drain portion on a channel portion side of a contact hole in the drain portion to a gate electrode is Lcontd, the following relationship is preferred:
0.8xc3x97Lldddxe2x89xa6Lcontdxe2x89xa61.2xc3x97Llddd.
Lcontd can be set to a range of xc2x120% of Llddd. This prevents any excessive increase in the contact resistance and also reduces the parasitic resistance based on factors such as the resistance of the LDD portion.
In a similar manner, when the LDD length of a source portion is Lldds and the distance from an edge of the source portion on a channel portion side of a contact hole in the source portion to a gate electrode is Lconts, the following relationship is preferred:
0.8xc3x97Llddsxe2x89xa6Lcontsxe2x89xa61.2xc3x97Lldds.
A sixteenth aspect of the invention provides a p-type thin-film transistor having a first and a second impurity-doped semiconductor films in which the implanted impurities are p-type. An n-type thin-film transistor is also provided having a first and a second impurity-doped semiconductor films in which the implanted impurities are n-type. This CMOS configuration permits faster device operation while consuming less power. An optimum thin-film semiconductor device is provided for the peripheral circuitry of a liquid crystal display device, for example.
The gate electrode length of the p-type thin-film transistor is preferably shorter than the gate electrode length of the n-type thin-film transistor. This balances the ON currents of the p-type and n-type thin-film transistors and allows implementation of high density circuits because the circuits can be configured with the same channel width.
The channel width of the n-type thin-film transistor is preferred to be smaller than the channel width of the p-type thin-film transistor. This enables an even further increase in speed because the ON currents are balanced. When all the gate electrode lengths are set to the minimum dimensions of the design rules, management of the fabrication process also becomes easier.
The gate electrode length of the p-type thin-film transistor and the gate electrode length of the n-type thin-film transistor are preferably approximately 5 xcexcm or less. This permits a further increase in the speed of the TFTS.
A seventeenth aspect of the invention provides a method of fabricating a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate. This method includes implanting an impurity by using a gate electrode as a mask and implanting an impurity by using a photoresist as a mask, where an impurity dose implanted by using the gate electrode as a mask is between approximately 1xc3x971013 cmxe2x88x922 and approximately 1xc3x971014 cmxe2x88x922. An impurity dose implanted by using the photoresist as a mask is between 5xc3x971014 cmxe2x88x922 and 1xc3x971016 cmxe2x88x922.
The impurities are implanted at a low energy but with a high throughput. Moreover, the LDD length is set freely so that the LDD structure is formed only as necessary in required areas. Thus the degree of freedom of circuit design is increased. Optimization of the implanted impurities is also facilitated.
An impurity is first implanted using the gate electrode as a mask. Then an insulation film is formed on the surface of the gate electrode. Finally, an impurity is again implanted to the semiconductor film.
Preferably, the method further includes forming an impurity-doped semiconductor film in an island shape in the source and the drain portions of the thin-film transistor. Then an intrinsic semiconductor film is formed on the island shaped impurity-doped semiconductor film. This improves the TFT characteristics by making the channel portion thin and lowers the contact resistance by making the source and the drain portions thick. This method provides a sufficiently large margin against overetching so that even when dry etching is used to open contact holes, yield is improved.
An insulation film on the gate electrode surface layer portion is either formed by thermal oxidation, anodic oxidation of the material of the gate electrode or by chemical vapor deposition methods. The chemical vapor deposition method forms an insulation film at a low temperature with a high throughput. Suitable combinations of these methods can be used to form a multi-layer insulation film, which further reduces defects.
An eighteenth aspect of the invention provides a display system using thin-film semiconductor devices comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the display system includes an active matrix portion and data and scan driver portions formed on the insulating material portion. The semiconductor film includes a first impurity-doped semiconductor film located in the source and the drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor.
The maximum impurity concentration of the second impurity-doped semiconductor film is in the range of between approximately 1xc3x971018 cmxe2x88x923 and approximately 1xc3x971019 cmxe2x88x923.
The data and scan driver portions use the LDD-type TFTs. Thus, high-speed operation is achieved while the voltage supply and current consumption are also low. The maximum impurity concentration of the first impurity-doped semiconductor film and/or the LDD length can be optimized by the invention further reducing the length of the channel.
A nineteenth aspect of the invention provides a clocked gate bidirectional shift register circuit for the data driver portion and the scan driver portion. This enables a simple method of reversing a screen image either horizontally or vertically, thus broadening the range of applications of the display device.
A twentieth aspect of the invention provides a plurality of shift register circuits. Each of the shift register circuits has a different clock signal phase. Gate circuits are also provided which receives outputs from the plurality of shift register circuits. The shift registers and gate circuits generate various timing pulses at high speed. For example, the serial input of data driver signals for the Japanese high-definition television (HDTV) system may be generated.
A twenty-first aspect of the invention provides a level-shifter circuit and a shift register circuit. The shift register circuit is driven at or below the TTL level. This ensures that the entire interface for external signals operates at or below the TTL level. This allows smaller, less expensive, less power-consuming external circuits to be implemented.
A twenty-second aspect of the invention provides a p-type thin-film transistor and an n-type thin-film transistor connected in series. This enables stable operation even when the difference between input and output voltages is large.
A twenty-third aspect of the invention provides that the data driver portion includes at least one shift register circuit, at least one video line and analog switches. One of outputs of the shift register circuit is input to a gate terminal of the analog switch, either directly or through a level-shifter circuit. An analog signal is supplied to each of picture elements in a dot-sequential manner. This enables the construction of an extremely compact data driver that has low power consumption permitting a compact display device to be implemented.
A twenty-fourth aspect of the invention provides that the data driver portion includes first-stage analog latches. Each of the analog latches is connected to at least one video line. The data driver portion also includes second-stage analog latches. Each of the second-stage analog latches has at least one input connected to an output from the first-stage analog latch. Analog buffers are included and each of the analog buffers is connected to an output from the second-stage analog latches. An analog signal is supplied to each of picture elements in a line-sequential manner which enables a large active-matrix type of LCD to be driven.
A twenty-fifth aspect of the invention provides that the data driver portion includes a group of n first-stage latches connected to n digital signal input lines. A group of n second-stage latches receives the outputs of the first-stage latches. A decoder is connected to 2n analog switch gates which receives the outputs of the second-stage latches. Digital signals are supplied to picture elements which enables the construction of a large-scale digital data driver. The large-scale digital data driver interfaces a digital signal with a multimedia display system using the latches and the decoders.
A twenty-sixth aspect of the invention provides that the display system includes a video signal amplification circuit for amplifying video signals output from a video signal generator. A timing controller is included for generating timing signals in synchronization with video signals output from the video signal generator. The data driver portion and the scan driver portion are driven by the timing signals which enable suppression of the power consumption of the entire system, thus making this display system suitable for use in portable electronic equipment.
A twenty-seventh aspect of the invention provides that the timing controller, the data driver portion, and the scan driver portion are driven at voltage levels equal to or below the TTL level which makes the external circuits extremely simple.
A twenty-eighth aspect of the invention provides that the timing controller is made from the thin-film semiconductor device which enables a system that is even more compact and inexpensive.
A twenty-ninth aspect of the invention provides that the video signal amplification circuit includes a signal frequency conversion circuit for converting a video signal into a plurality of low-frequency signals or a gamma correction circuit which improves the horizontal resolution and also increase grayscale levels.
A thirtieth aspect of the invention provides that the video signal amplification circuit comprises thin-film semiconductor devices. When the video signal amplification circuit is formed using the thin-film semiconductor devices provided by the invention, the display system is compact and inexpensive.
A thirty-first aspect of the invention provides a thin-film semiconductor device comprising a non-single-crystal semiconductor film formed on an insulating material portion which covers at least one portion of a surface of a substrate, where the semiconductor film is deposited by a chemical vapor deposition method under conditions that retard the generation rate of nuclei that act as seeds for film formation and accelerate the growth rate of islands formed from the nuclei. The semiconductor film includes a first impurity-doped semiconductor film located in the source and the drain portions of a thin-film transistor. A high-resistance second impurity-doped semiconductor film is located in at least one area between the drain and the channel portions or between the source and the channel portions of the thin-film transistor.
The semiconductor film is formed while the nucleus generation rate is retarded and the island growth rate is accelerated allowing an LDD-type TFT circuit to be implemented using this semiconductor film. Further, an increase in carrier mobility, a reduction in contact resistance in the channel length of the transistor and an increase in the breakdown voltage is achieved allowing a high-speed thin-film semiconductor device to be implemented that is not inferior to a single-crystal MOSFET. Since the island regions forming the semiconductor film are extremely large, the resultant polycrystalline configuration after annealing has an extremely low level of crystal defects. Therefore, the electric resistance of the LDD portion is reduced and the ON current is further improved. The maximum impurity concentration of the first and second impurity-doped semiconductor films and/or the LDD length is optimized by the invention enabling a further reduction in the length of the channel.
The maximum impurity concentration of the second impurity-doped semiconductor film is optimized by setting the maximum impurity concentration between approximately 2xc3x971017 cmxe2x88x923 and approximately 1xc3x971019 cmxe2x88x923 which broadens the range of the maximum impurity concentration. Since the semiconductor film is formed while the nucleus generation rate is retarded and the island growth rate is accelerated, the number of crystal defects is reduced thus lowering the electric resistance of the LDD portion. Therefore, the sheet resistance of the LDD portion is low even when the maximum impurity concentration of the LDD portion is low. Thus, the lower limit of the maximum impurity concentration of the LDD portion can be set as low as approximately 2xc3x971017 cmxe2x88x923.
The LDD length is optimized to between approximately 0.3 xcexcm and approximately 4 xcexcm, thus broadening the range of the LDD length. Since the semiconductor film is formed while the nucleus generation rate is retarded and the island growth rate is accelerated, the semiconductor film has few grain boundaries. Thus, impurities are restrained from increased diffusion along the grain boundaries. Therefore, the minimum LDD length can be shortened to approximately 0.3 xcexcm which enables a further reduction in the parasitic resistance of the LDD portion.
A thirty-second aspect of the invention provides that the second impurity-doped semiconductor film is arranged over the entire region of the source and the drain portions of a p-type thin-film transistor having a p-type impurity-doped semiconductor film. The sheet resistance of the second impurity-doped semiconductor film is reduced although the impurity is implanted at low concentration. Thus, the step of implanting an impurity to high concentration in the p-type thin-film transistor can be omitted and the entire region of the source and the drain portions can be made from the low-concentration second impurity-doped semiconductor film. This eliminates one processing step, such as a photoprocessing step, permitting a higher density integrated circuits.